sn54als563b, SN74ALS563B octal d-type transparent latches with 3-state outputs sdas163a december 1982 revised january 1995 copyright ? 1995, texas instruments incorporated 1 post office box 655303 ? dallas, texas 75265 ? 3-state buffer-type outputs drive bus lines directly ? bus-structured pinout ? package options include plastic small-outline (dw) packages, ceramic chip carriers (fk), standard plastic (n) and ceramic (j) 300-mil dips, and ceramic flat (w) packages description these 8-bit d-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. they are particularly suitable for implementing buffer registers, i/o ports, bidirectional bus drivers, and working registers. while the latch-enable (le) input is high, the q outputs follow the complements of data (d) inputs. when le is taken low, the outputs are latched at the inverses of the levels set up at the d inputs. a buffered output-enable (oe ) input places the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines significantly. the high-impedance state and increased high logic level provide the capability to drive bus lines without interface or pullup components. oe does not affect internal operations of the latches. old data can be retained or new data can be entered while the outputs are in the high-impedance state. the sn54als563b is characterized for operation over the full military temperature range of 55 c to 125 c. the SN74ALS563B is characterized for operation from 0 c to 70 c. function table (each latch) inputs output oe le d q l h h l l hh h l lx q 0 h x x z 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oe 1d 2d 3d 4d 5d 6d 7d 8d gnd v cc 1q 2q 3q 4q 5q 6q 7q 8q le sn54als563b ...j or w p ackage SN74ALS563B . . . dw or n package (top view) 3212019 910111213 4 5 6 7 8 18 17 16 15 14 2q 3q 4q 5q 6q 3d 4d 5d 6d 7d sn54als563b . . . fk package (top view) 2d 1d oe 8q 7q 1q 8d gnd le v cc production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
sn54als563b, SN74ALS563B octal d-type transparent latches with 3-state outputs sdas163a december 1982 revised january 1995 2 post office box 655303 ? dallas, texas 75265 logic symbol 2 logic diagram (positive logic) oe 1d 2 1d 3 2d 4 3d 5 4d 6 5d c1 11 le 19 18 17 16 15 14 13 12 7 6d 8 7d 9 8d en 1 oe le 1d 1q 1 11 2 19 to seven other channels c1 1d 1q 2q 3q 4q 5q 6q 7q 8q 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 3 supply voltage, v cc 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage, v i 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage applied to a disabled 3-state output 5.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a : sn54als563b 55 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . SN74ALS563B 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions sn54als563b SN74ALS563B unit min nom max min nom max unit v cc supply voltage 4.5 5 5.5 4.5 5 5.5 v v ih high-level input voltage 2 2 v v il low-level input voltage 0.7 0.8 v i oh high-level output current 1 2.6 ma i ol low-level output current 12 24 ma t w pulse duration, le high 15 15 ns t su setup time, data before le 20 10 ns t h hold time, data after le 12 10 ns t a operating free-air temperature 55 125 0 70 c
sn54als563b, SN74ALS563B octal d-type transparent latches with 3-state outputs sdas163a december 1982 revised january 1995 3 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions sn54als563b SN74ALS563B unit parameter test conditions min typ 2 max min typ 2 max unit v ik v cc = 4.5 v, i i = 18 ma 1.2 1.2 v v cc = 4.5 v to 5.5 v, i oh = 0.4 ma v cc 2 v cc 2 v oh v cc =45v i oh = 1 ma 2.4 3.3 v v cc = 4 . 5 v i oh = 2.6 ma 2.4 3.2 v ol v cc =45v i ol = 12 ma 0.25 0.4 0.25 0.4 v v ol v cc = 4 . 5 v i ol = 24 ma 0.35 0.5 v i ozh v cc = 5.5 v, v o = 2.7 v 20 20 m a i ozl v cc = 5.5 v, v o = 0.4 v 20 20 m a i i v cc = 5.5 v, v i = 7 v 0.1 0.1 ma i ih v cc = 5.5 v, v i = 2.7 v 20 20 m a i il v cc = 5.5 v, v i = 0.4 v 0.1 0.1 ma i o 3 v cc = 5.5 v, v o = 2.25 v 20 112 30 112 ma outputs high 10 17 10 17 i cc v cc = 5.5 v outputs low 16 26 16 26 ma outputs disabled 17 29 17 29 2 all typical values are at v cc = 5 v, t a = 25 c. 3 the output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, i os . switching characteristics (see figure 1) parameter from (input) to (output) v cc = 4.5 v to 5.5 v, c l = 50 pf, r1 = 500 w , r2 = 500 w , t a = min to max unit sn54als563b SN74ALS563B min max min max t plh d q 3 26 3 18 ns t phl d q 3 15 3 14 ns t plh le q 8 29 6 22 ns t phl le q 4 22 6 21 ns t pzh oe q 4 25 3 18 ns t pzl oe q 4 21 4 18 ns t phz oe q 2 12 1 10 ns t plz oe q 3 22 1 15 ns for conditions shown as min or max, use the appropriate value specified under recommended operating conditions.
sn54als563b, SN74ALS563B octal d-type transparent latches with 3-state outputs sdas163a december 1982 revised january 1995 4 post office box 655303 ? dallas, texas 75265 parameter measurement information series 54als/74als and 54as/74as devices t phz t plz t phl t plh 0.3 v t pzl t pzh t plh t phl load circuit for 3-state outputs from output under test test point r1 s1 c l (see note a) 7 v 1.3 v 1.3 v 1.3 v 3.5 v 3.5 v 0.3 v 0.3 v t h t su voltage waveforms setup and hold times timing input data input 1.3 v 1.3 v 3.5 v 3.5 v 0.3 v 0.3 v high-level pulse low-level pulse t w voltage waveforms pulse durations input out-of-phase output (see note c) 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 3.5 v 3.5 v 0.3 v 0.3 v v ol v oh v oh v ol output control (low-level enabling) waveform 1 s1 closed (see note b) waveform 2 s1 open (see note b) 0 v v oh v ol 3.5 v in-phase output 0.3 v 1.3 v 1.3 v voltage waveforms propagation delay times voltage waveforms enable and disable times, 3-state outputs r2 v cc r l test point from output under test c l (see note a) load circuit for open-collector outputs load circuit for bi-state totem-pole outputs from output under test test point c l (see note a) r l r l = r1 = r2 notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. when measuring propagation delay items of 3-state outputs, switch s1 is open. d. all input pulses have the following characteristics: prr 1 mhz, t r = t f = 2 ns, duty cycle = 50%. e. the outputs are measured one at a time with one transition per measurement. figure 1. load circuits and voltage waveforms
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